View Proposal

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Proposer

Adam Sampson

Title

Security extensions for RISC-V

Goal

Experiment with changes to the RISC-V architecture to improve software security

Description

RISC-V is a modern RISC architecture based on open-source principles; there's a core of instructions and a collection of extensions that provide additional facilities (e.g. vector maths). There are existing high-quality toolchains and software emulators for it - you don't need RISC-V hardware to work with it. Projects like CHERI have experimented with extending existing computer architectures to provide better security facilities - CHERI adds pointer bounds to the ARMv8 architecture. Design an extension to RISC-V to provide similar facilities, or to improve software security in other ways (e.g. bounds checking, pointer authentication, untrusted data tracking...). Implement this in an emulator to demonstrate that it can be used to detect errors in programs. (A previous student experimented with pointer authentication successfully, so maybe try a different approach.)

Resources

Background

Url

Difficulty Level

High

Ethical Approval

None

Number Of Students

1

Supervisor

Adam Sampson

Keywords

risc-v, security, cpu, architecture, cheri

Degrees

Bachelor of Science in Computer Science
Bachelor of Science in Computer Systems
Master of Engineering in Software Engineering
Master of Science in Computer Science for Cyber Security
Master of Science in Computing (2 Years)
Master of Science in Information Technology (Software Systems)
Master of Science in Network Security
Master of Science in Software Engineering
Bachelor of Science in Computing Science
Bachelor of Engineering in Robotics
Bachelor of Science in Computer Science (Cyber Security)