View Proposal

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Proposer

Rob Stewart

Title

Targeting FPGAs with parallel functional languages

Goal

Develop a Verilog backed for the functional language Accelerate

Description

FPGAs are reconfigurable chips and offer promise of very high performance, low powered targets for accelerated computation. They have potential in many domains including High Performance Computing, Cloud Computing, embedded processing and autonomous robotics. FPGAs are usually programmed at very low levels with hardware description languages, and sometimes at the higher level C language. High level parallel array processing languages like APL, Accelerate and Chapel abstract above hardware, usually targeting multicore CPUs and GPUs. This project will involve writing an FPGA backend for the Accelerate DSL, an embedded language in Haskell, Backend options are OpenCL or C++, from which High Level Synthesis tools will generate FPGA hardware designs. This is a compiler research project that will establish how to produce high performance (outperforming parallel CPUs and GPUs) and efficient hardware from very high level array processing codes.

Resources

Background

Url

External Link

Difficulty Level

Challenging

Ethical Approval

None

Number Of Students

1

Supervisor

Rob Stewart

Keywords

Degrees